1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor and a method of manufacturing the same, and in particular to a semiconductor device having a capacitor in which a capacitor dielectric layer made of a material having a high dielectric constant is interposed between two electrodes as well as a method of manufacturing the same.
2. Description of the Background Art
Demands for semiconductor memory devices have been rapidly increased owing to rapid and wide spread of information equipments such as computers. Regarding a function, devices having a large-scale storage capacity and a high operation speed have been demanded. In view of this, technical development has been made for improving a density, a responsibility and a reliability of semiconductor memory devices.
DRAMs (Dynamic Random Access Memories) are well known as a kind of semiconductor memory devices allowing random input/output of storage information. The DRAM is formed of a memory cell array, which is a storage region storing large storage information, and a peripheral circuitry required for external input and output. The memory cell array occupies a large area on a semiconductor chip of the DRAM having the above structure. The memory cell array is provided with a plurality of memory cells each storing unit storage information and arranged in a matrix form. The memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto, and hence is well known as a memory cell of a one-transistor and one-capacitor type. Since the memory cell thus constructed has a simple structure, the density or degree of integration of memory cells can be increased easily, and hence is widely used in a DRAM of a large capacity.
For increasing the integration density of the DRAM, it is unavoidably required to reduce the memory size. The reduction in memory size results in reduction in planar area occupied by the capacitor. This reduces a quantity of electric charges accumulatable in the capacitor (i.e., a quantity of charges accumulatable in the memory cell of one bit) so that the DRAM may not operate stably as a storage region, resulting in lowering of a reliability.
For presenting such instability in operation of the DRAM, it is necessary to increase the capacity of the capacitor formed in a limited planar area. It has been studied to increase the dielectric constant of the capacitor dielectric layer as a measure for increasing the capacitor capacity while keeping a relatively simple form of the capacitor.
For increasing the dielectric constant of the capacitor dielectric layer, the capacitor dielectric layer may be made of a material having a high dielectric constant, i.e., a so-called high dielectric material. This high dielectric material generally has a dielectric constant which is several to hundreds of times larger than that of a silicon oxide film. By using the high dielectric material as the capacitor dielectric layer, the capacity can be easily increased while maintaining a relatively simple form of the capacitor.
Such high dielectric material may be selected from a group containing, for example, tantalum pentoxide (Ta.sub.2 O.sub.5), barium strontium titanate (Ba.sub.x Sr.sub.(1-x) TiO.sub.3 (0.ltoreq.x.ltoreq.1), which will be simply referred to as "BST" hereinafter), lead lanthanum zirconate titanate (Pb.sub.x La.sub.(1-x) Zr.sub.y Ti.sub.(1-y) O.sub.3 (0.ltoreq.x .ltoreq.1, 0.ltoreq.y .ltoreq.1), which will be simply referred to as "PLZT"), strontium bismuthate tantalate (SrBi.sub.2 Ta.sub.2 O.sub.8, which will be simply referred to as "SBT"), lead zirconate titanate which will be simply referred to as "PZT", strontium titanate which will be referred to as "STO", and barium titanate which will be simply referred to as "BTO".
FIG. 26 is a cross section schematically showing a structure of a semiconductor device having a capacitor in the prior art. Referring to FIG. 26, a plurality of memory cells of a DRAM is formed at regions of a silicon substrate 11 isolated from each other by an isolating and insulating layer 13. Each memory cell has a transfer gate transistor 20 and a capacitor 110, and therefore is of a one-transistor and one-capacitor type.
Each transfer gate transistor 20 has a pair of source/drain regions 15, a gate insulating layer 17 and a gate electrode layer 19. Paired source/drain regions 15 are formed at the surface of silicon substrate 11 with a space from each other. Gate electrode layer 19 is formed on a region located between paired source/drain regions 15 with gate insulating layer 17 therebetween.
A conductive layer 21 forming a bit line is connected to one of paired source/drain regions 15.
Transfer gate transistor 20 and bit line 21 are covered with an interlayer insulating film 23. Interlayer insulating film 23 is provided with contact holes 23a, each of which reaches the other of corresponding paired source/drain regions 21, and is filled with an electrically conductive plug layer 25. A capacitor 10 is electrically connected to source/drain region 15 through plug layer 25.
Each capacitor 110 has a lower electrode layer (storage node) 101, a capacitor dielectric layer 107 and an upper electrode layer (cell plate) 109. Lower electrode layer 101 is electrically connected to plug layer 25 through a barrier metal layer 103. When plug layer 25 has barrier property, barrier metal layer 103 is unnecessary. Side surfaces of lower electrode layer 101 and barrier metal layer 103 are covered with a frame insulating layer 105. When capacitor dielectric layer 107 has good coverage characteristic, frame insulating layer 105 on the side surface of lower electrode layer 101 may not be provided. Capacitor insulating layer 107 is made of a material containing the high dielectric material already described, and covers the top surface of lower electrode layer 101. Upper electrode layer 109 is opposed to lower electrode layer 101 through capacitor dielectric layer 107.
Barrier metal layer 103 serves to prevent diffusion of impurity contained in plug layer 25 into lower electrode layer 101 and improve the adhesion between lower electrode layer 101 and interlayer insulating layer 23, and is made of, e.g., TiN (titanium nitride).
All the foregoing high dielectric materials which can be used in capacitor dielectric layer 107 contain oxide of transition metal. The transition metal has such a feature that its oxidation number may take on various values. However, the oxide of a low oxidation number is generally electrically conductive. If the transition metal is to be used as capacitor dielectric layer 107, therefore, the oxide must keep a high oxidation number, and a particular attention must be given to oxygen deficit in the material and, particularly, at the vicinity of a boundary surface with respect to the electrode material.
If an easily oxidizable material such as Si (silicon) or Ti (titanium) were used, electrodes 101 and 109 would cause an oxidation-reduction reaction with respect to capacitor dielectric layer 107 so that a leak current would increase due to oxygen deficit at the vicinity of electrodes 101 and 109. Accordingly, electrodes 101 and 109 in the prior art are made of rare metal or electrically conductive oxide, which are materials having a high resistance against oxidation.
Particularly, platinum has been widely used for study and research, because the platinum has a lattice constant which is close to crystal lattice constants of PZT and BST used in capacitor dielectric layer 107, and therefore allows easy production of capacitor dielectric layer 107 having a high crystallinity owing to heteroepitaxial growth. As can be understood from the fact that the platinum may be used as catalyst, however, it is very active with respect to a surface reaction. Therefore, it increases the speed of reduction reaction of capacitor dielectric layer 107 in a reducing atmosphere, so that the insulating property of capacitor dielectric layer 107 is impaired. This fact has recently been recognized.
FIG. 27 shows leak current characteristics of a capacitor produced in such a manner that a BST film (capacitor dielectric layer) was formed on a platinum electrode formed on a silicon oxide film by sputtering at a temperature of 400.degree. C. in an argon gas, and then a platinum electrode was formed by patterning on the BST film. The BST film had a film thickness of 60 nm and was formed under the conditions of a temperature from 400 to 600.degree. C., a pressure from 0.2 to 0.8 Pa and a flow ratio O.sub.2 /(Ar+O.sub.2) smaller than 0.5.
Application of this film to a DRAM will now be discussed. If a power supply voltage Vcc of a DRAM is 3.3 V, a voltage of 1.65 V which is a half of Vcc is applied to a capacitor dielectric layer. As can be seen from FIG. 27, however, a leak current density of the capacitor with this voltage significantly exceeds 100 nA/cm.sup.2 which is a specified request value. Although this capacitor has a simple MIM structure, it is subjected to various kinds of heat treatments in the actual DRAM process after formation of the capacitor, and is also subjected to hydrogen annealing for improving transistor characteristics. For producing a film which endures such thermal stresses and annealing in a reduction atmosphere, it is furthermore required to suppress oxygen deficit at the boundary between the electrode and the capacitor dielectric layer, and improve the crystallinity.
Japanese Patent Laying-Open No. 5-343616 (1993) has disclosed a technique for preventing occurrence of a leak current due to the oxygen deficit. According to this publication, oxygen is contained at least in a region, which is in contact with a capacitor dielectric layer, of one of electrodes of a capacitor, and thereby occurrence of a leak current due to the oxygen deficit is prevented. This publication has also disclosed manners of introducing oxygen into the electrode by ion-implanting oxygen into the electrode and by exposing the electrode to oxygen plasma. Japanese Patent Laying-Open No. 6-65715 has disclosed a manner of depositing a lower electrode layer containing oxygen introduced thereinto by sputtering in an atmosphere containing oxygen.
However, the ion implantation is a manner performed by physically introducing oxygen ions into the electrode, so that the ion implantation disturbs the crystallinity at the surface of the electrode. Also, the crystallinity of a high dielectric material, which forms the capacitor dielectric layer, is easily affected by a crystallinity of a base or underlying material. Therefore, the layer of the high dielectric material, which is formed on the surface of the electrode having a disturbed crystallinity, suffers from such problems that the crystallinity of the high dielectric material layer is disturbed, and a perovskite structure cannot be obtained, resulting in a problem that the leak current in capacitor increases.
The implantation of ions and the exposure to the oxygen plasma require additional steps, which complicates the manufacturing process.
According to Japanese Patent Laying-Open No. 6-65715, the sputtering for the lower electrode layer is performed with a substrate temperature of 500.degree. C. or more. Therefore, the structure in which the lower electrode layer is formed on the barrier metal layer suffers from such problems that the lower electrode layer may be peeled off and that current leak may occur due to concentration of an electric field. This will now be discussed below more in detail.
FIGS. 28 to 31 are step diagrams for showing the above problems. Referring first to FIG. 28, interlayer insulating layer 23 covering transfer gate transistor 20 and others is formed, and then barrier metal layer 103 and lower electrode layer 101 are successively formed. When the substrate is set to a high temperature of 500.degree. C. or more during the sputtering for lower electrode layer 101, barrier metal layer 103 is oxidize so that a convexity 103a is locally formed at the surface thereof.
Referring to FIG. 29, therefore, convexity 103a grown to a considerable extent is present when deposition of the lower electrode layer 101 is completed, and a stress due to convexity 103a causes cracking or the like at lower electrode layer 101.
Referring to FIG. 30, lower electrode layer 101 and barrier metal layer 103 masked with a resist pattern 151 are then patterned. Lower electrode layer 101 having cracks or the like may be locally peeled of in a step of removing resist pattern 151 after the patterning or a subsequent washing step.
Referring to FIG. 31, a convexity 101a is formed at the surface of lower electrode layer 101 due to convexity 103a formed at the surface of barrier metal layer 103. Capacitor insulating layer 107 and upper electrode 109 deposited by a sputtering method covers convexity 101a. Since the sputtering method cannot achieve a good property of covering a stepped portion, the thickness of capacitor dielectric layer 107 decreases at the vicinity (a region P) of the lower end of convexity 101a, and a peak or sharp portion 109a is formed at upper electrode 109. Since the electric field is concentrated at peak 109a, current leak is liable to occur due to this concentration and reduction in thickness of capacitor dielectric film 107.